#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_INTEL64
comment "intel64 Configuration Options"

choice
	prompt "Intel64 Chip Selection"
	default ARCH_CHIP_INTEL64_QEMU

config ARCH_CHIP_INTEL64_QEMU
	bool "Intel64 QEMU"

config ARCH_CHIP_INTEL64_CUSTOM
	bool "Custom Intel64 chip"

endchoice # "Intel64 Chip Selection"

config ARCH_INTEL64_HAVE_TSC
	bool

config ARCH_INTEL64_CACHE_LINESIZE
	int "Cache line size (hardcoded)"
	depends on ARCH_DCACHE || ARCH_ICACHE
	default 64
	---help---
		Cache line size. If set to 0, we read the value from CPUID,
		(Probably) all new Intel CPUs have this value equal to 64.

config ARCH_INTEL64_DCACHE_SIZE
	int "Data cache line size (L1d)"
	depends on ARCH_DCACHE
	default 0
	---help---
		Data cache line size (L1d). If set to 0, we read the value from CPUID.

config ARCH_INTEL64_ICACHE_SIZE
	int "Instruction cache line size (L1i)"
	depends on ARCH_ICACHE
	default 0
	---help---
		Instruction cache line size (L1i). If set to 0, we read the value from CPUID.

config ARCH_INTEL64_HAVE_CLWB
	bool "CLWB support"
	default n
	---help---
		Select to enable the use of CLWB to write back cache line

choice
	prompt "System Timer Source"
	default ARCH_INTEL64_TSC_DEADLINE
	---help---
		Choose which hardware resource will drive NuttX
		system time

config ARCH_INTEL64_TSC_DEADLINE
	bool "TSC DEADLINE timer support"
	select ARCH_INTEL64_HAVE_TSC
	---help---
		Select to enable the use of TSC DEADLINE timer of x86_64

config ARCH_INTEL64_TSC
	bool "TSC APIC timer support"
	select ARCH_INTEL64_HAVE_TSC
	---help---
		Select to enable the use of TSC APIC timer of x86_64

config ARCH_INTEL64_HPET_ALARM
	bool "HPET timer alarm support"
	depends on ALARM_ARCH
	---help---
		With this option you can enable ALARM_ARCH features that works on top of
		the HPET timer instance. This is an alternative method to TSC timer to
		provide the system clock.

endchoice # System Timer Source

if ARCH_INTEL64_TSC_DEADLINE

config ARCH_INTEL64_CORE_FREQ_KHZ
	int "CPU Core frequency in kHz"
	default 2000000
	---help---
		The CPU Core frequency (without Turbo boost). This is used
		to set the TSC deadline timer frequency. If set to 0 we try to get
		frequency from CPUID.

config ARCH_INTEL64_TSC_FREQ_VMWARE
	bool "Use CPUID 0x40000010 to get CPU Core frequency"
	default n
	depends on ARCH_INTEL64_CORE_FREQ_KHZ = 0
	---help---
		Use CPUID 0x40000010 defined by VMware to get CPU Core frequency
		in virtualized environments.
endif

if ARCH_INTEL64_TSC

config ARCH_INTEL64_APIC_FREQ_KHZ
	int "APIC timer frequency in kHz"
	default 2000000
	---help---
		The APIC timer frequency. This is used to set the APIC timer
		frequency in case of no TSC DEADLINE timer is available.

endif

config INTEL64_HPET
	bool "HPET timer support"
	default n
	---help---
		Select to enable the HPET timer support

if INTEL64_HPET

config INTEL64_HPET_BASE
	hex "HPET timer base address"
	default 0xfed00000
	---help---
		Configure base address for HPET. In the future, we can get this address from
		the ACPI table if ACPI support is enabled.

config INTEL64_HPET_32BIT
	bool "HPET is 32bit"
	default n
	---help---
		Configure HPET in 32-bit mode.

config INTEL64_HPET_FSB
	bool "HPET use FSB for interrupt"
	default n
	---help---
		Use FSB for interrupt (works like MSI interrupts).

config ARCH_INTEL64_HPET_ALARM_CHAN
	int "HPET timer alarm channel"
	depends on ARCH_INTEL64_HPET_ALARM
	default 0

config INTEL64_HPET_CHANNELS
	int "HPET timer supported channels"
	default 2
	range 1 3
	---help---
		Configure the number of supported HPET channels (called HPET timers
		in HPET spec). We use HPET legacy replacement for interrupts which
		means that Timer 0 and Timer 1 interrupts are hardcoded, but Timer 2
		needs additional attention to configure interrupt routing.
		Timer 2 will most likely not work with QEMU.

config INTEL64_HPET_MIN_DELAY
	int "HPET minimum supported delay in micro-seconds"
	default 1000
	---help---
		HPET use free running up-counter and a comparators which generate events
		only on a equal event. This can results in event miss if we set too small
		delay. In that case we must set a minimum value for delay that always work.
		For the QEMU target this value should be as high as 1000, but for real
		hardware it may go much lower (for i7-1255U CPU it works with values <10).

endif # INTEL64_HPET

config INTEL64_ONESHOT
	bool "Oneshot timer support"
	select INTEL64_HPET
	default n
	---help---
		Select to enable the oneshot timer support

if INTEL64_ONESHOT

config INTEL64_ONESHOT_MAXTIMERS
	int "Maximum number of oneshot timers"
	default 1
	range 1 3
	---help---
		Determines the maximum number of oneshot timers that can be
		supported.

endif

config ARCH_INTEL64_HAVE_PCID
	bool "PCID support"
	default y
	---help---
		Select to enable the use of PCID to reduce TLB flush

config ARCH_INTEL64_HAVE_RDRAND
	bool "RDRAND support"
	default y
	---help---
		Select to enable the use of RDRAND for /dev/random

config ARCH_INTEL64_DISABLE_INT_INIT
	bool "Disable Initialization of 8259/APIC/IO-APIC"
	default n
	---help---
		Select to disable all initialization related to interrupt
		controllers. This is necessary if those are already
		initialized, i.e. Jailhouse system.

config ARCH_INTEL64_DISABLE_CET
	bool "Disable CET completely"
	---help---
		Intel CET (Control-flow Enforcement Technology) is a hardware
		enhancement aimed at mitigating the Retpoline vulnerability.
		It inserts the endbr64 instruction at the beginning of functions,
		which may impact CPU branch prediction performance.

config ARCH_INTEL64_DISABLE_VECTORIZE
	bool "Disable vectorize completely"
	---help---
		Disable the compiler from vectorizing code optimization during compilation

endif
